Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures

Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that leverages repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A novel configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration. When applied to a two-level cache and TLB hierarchy at 0.1

• Type: Conference
• Year: 2000
• Where: MICRO
• Authors: Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
• Keywords: Cache Hierarchy, Hardware, Memory Hierarchy, Memory Hierarchy Design, MICRO 2000