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» Architectural Considerations for Energy Efficiency
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DATE
2006
IEEE
100views Hardware» more  DATE 2006»
14 years 2 months ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer
ICCD
2008
IEEE
136views Hardware» more  ICCD 2008»
14 years 5 months ago
A resource efficient content inspection system for next generation Smart NICs
— The aggregate power consumption of the Internet is increasing at an alarming rate, due in part to the rapid increase in the number of connected edge devices such as desktop PCs...
Karthik Sabhanatarajan, Ann Gordon-Ross
SOSP
2001
ACM
14 years 5 months ago
Building Efficient Wireless Sensor Networks with Low-Level Naming
In most distributed systems, naming of nodes for low-level communication leveragestopologicallocation(such as node addresses) and is independentof any application. In this paper, ...
John S. Heidemann, Fabio Silva, Chalermek Intanago...
VLSISP
2008
129views more  VLSISP 2008»
13 years 8 months ago
Architecture and Evaluation of an Asynchronous Array of Simple Processors
Abstract-- This paper presents the architecture of an Asynchronous Array of simple Processors (AsAP), and evaluates its key architectural features as well as its performance and en...
Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, O...
TON
2010
93views more  TON 2010»
13 years 3 months ago
Design and field experimentation of an energy-efficient architecture for DTN throwboxes
Disruption tolerant networks rely on intermittent contacts between mobile nodes to deliver packets using a storecarry-and-forward paradigm. We earlier proposed the use of throwbox ...
Nilanjan Banerjee, Mark D. Corner, Brian Neil Levi...