Sciweavers

294 search results - page 31 / 59
» Architectural Exploration and Optimization of Local Memory i...
Sort
View
SIES
2008
IEEE
14 years 2 months ago
Performance evaluation of a java chip-multiprocessor
—Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP. It is a symmetric shared-m...
Christof Pitter, Martin Schoeberl
HPCA
2012
IEEE
12 years 3 months ago
System-level implications of disaggregated memory
Recent research on memory disaggregation introduces a new architectural building block—the memory blade—as a cost-effective approach for memory capacity expansion and sharing ...
Kevin T. Lim, Yoshio Turner, Jose Renato Santos, A...
ASPDAC
2000
ACM
92views Hardware» more  ASPDAC 2000»
14 years 12 days ago
Co-synthesis with custom ASICs
- This paper introduces the first hardwarekoftware co-synthesis algorithm that optimizes the implementations of ASICs that are used as processing elements for the embedded systems....
Yuan Xie, Wayne Wolf
LCTRTS
2007
Springer
14 years 2 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
DATE
2006
IEEE
95views Hardware» more  DATE 2006»
13 years 11 months ago
Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications
Network applications are becoming increasingly popular in the embedded systems domain requiring high performance, which leads to high energy consumption. In networks is observed t...
Alexandros Bartzas, Stylianos Mamagkakis, Georgios...