29 search results - page 2 / 6 » Architectural Exploration of the ADRES Coarse-Grained Reconf... |
FPL
2000
Springer
14 years 2 months ago
2000
Springer
Coarse-grain reconfigurable architectures have been a matter of intense research in the last few years. They promise to be more adequate for computational tasks due to their better...
VLSISP
2008
13 years 10 months ago
2008
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
ERSA
2009
13 years 8 months ago
2009
We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...
FPL
2010
Springer
13 years 8 months ago
2010
Springer
Abstract--Efficient storage in spatial processors is increasingly important as such devices get larger and support more concurrent operations. Unlike sequential processors that rel...
FCCM
2005
IEEE
14 years 4 months ago
2005
IEEE
This paper investigates the impact of the local and global register file architecture on a reconfigurable system based on the ADRES architecture [3]. The register files consume a s...