Sciweavers

60 search results - page 9 / 12
» Architectural Frameworks for MPP Systems on a Chip
Sort
View
EUC
2005
Springer
14 years 1 months ago
On Tools for Modeling High-Performance Embedded Systems
Abstract. Most of the new embedded systems require high performance processors at low power. To cater to these needs, most semiconductor companies are designing multi-core processo...
Anilkumar Nambiar, Vipin Chaudhary
GECCO
2007
Springer
268views Optimization» more  GECCO 2007»
14 years 2 months ago
Synthesis of analog filters on an evolvable hardware platform using a genetic algorithm
This work presents a novel approach to filter synthesis on a field programmable analog array (FPAA) architecture using a genetic algorithm (GA). First, a Matlab model of the FPA...
Joachim Becker, Stanis Trendelenburg, Fabian Henri...
ASPDAC
2009
ACM
115views Hardware» more  ASPDAC 2009»
14 years 2 months ago
Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform
— Multiprocessors on a chip are the reality of these days. Semiconductor industry has recognized this approach as the most efficient in order to exploit chip resources, but the ...
Antonino Tumeo, Marco Branca, Lorenzo Camerini, Ma...
ASPDAC
2004
ACM
120views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Compiler based exploration of DSP energy savings by SIMD operations
— The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting their special architecture features. Beside the ...
Markus Lorenz, Peter Marwedel, Thorsten Dräge...
IPPS
2006
IEEE
14 years 1 months ago
Reducing the associativity and size of step caches in CRCW operation
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
M. Forsell