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JMLR
2006
80views more  JMLR 2006»
13 years 7 months ago
Using Machine Learning to Guide Architecture Simulation
An essential step in designing a new computer architecture is the careful examination of different design options. It is critical that computer architects have efficient means by ...
Greg Hamerly, Erez Perelman, Jeremy Lau, Brad Cald...
HPCA
2008
IEEE
14 years 2 months ago
Prediction of CPU idle-busy activity pattern
Real-world workloads rarely saturate multi-core processor. CPU C-states can be used to reduce power consumption during processor idle time. The key unsolved problem is: when and h...
Qian Diao, Justin J. Song
CF
2009
ACM
14 years 2 months ago
A light-weight fairness mechanism for chip multiprocessor memory systems
Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...
Magnus Jahre, Lasse Natvig
ASAP
2008
IEEE
161views Hardware» more  ASAP 2008»
13 years 9 months ago
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posterio...
Yang Sun, Yuming Zhu, Manish Goel, Joseph R. Caval...
DEBS
2007
ACM
13 years 9 months ago
Identification of suspicious, unknown event patterns in an event cloud
This paper describes an approach to detect unknown event patterns. In this context, an event is not only something that happens, but also something that can be analysed. This task...
Alexander Widder, Rainer von Ammon, Philippe Schae...