Prediction of CPU idle-busy activity pattern

Real-world workloads rarely saturate multi-core processor. CPU C-states can be used to reduce power consumption during processor idle time. The key unsolved problem is: when and how to use which Cstate. We propose a machine learning prediction method and usage model. We evaluate this model with idle traces collected on dual-core and quad-core processor, and find this method can well predict CPU’s activity pattern at the error level not exceeding 4%. Compared with existing OS C-state policy, it results in 12% additional CPU power saving and 2% performance improvement. In industry, 12% power saving for any processor is very significant improvement. SPECWeb (which we used consists of 3 different benchmarks -- We consistently see doubledigit power saving) is representative “front-end” server workload – it takes >60% DP server market segment share.

• Type: Conference
• Year: 2008
• Where: HPCA
• Authors: Qian Diao, Justin J. Song
• Keywords: Computer Architecture, HPCA 2008, Power Saving, Processor Idle Time, Saturate Multi-core Processor