36 search results - page 5 / 8 » Architectural Power Optimization by Bus Splitting |
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class o...
MOBICOM
2009
ACM
14 years 2 months ago
2009
ACM
We consider the problem of efficient link-layer multicasting in wireless networks with switched beamforming antennas. The inherent tradeoff between multicasting and beamforming ...
LCTRTS
2004
Springer
14 years 27 days ago
2004
Springer
The overhead in terms of code size, power consumption and execution time caused by the use of precompiled libraries and separate compilation is often unacceptable in the embedded ...
DATE
2003
IEEE
14 years 25 days ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
ESTIMEDIA
2008
Springer
13 years 9 months ago
2008
Springer
The relentless increase in multimedia embedded system application requirements as well as improvements in IC design technology have motivated the deployment of chip multiprocessor ...