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» Architectural Specifications in CASL
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SIGPLAN
2008
15 years 5 months ago
A parallel dynamic compiler for CIL bytecode
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...
Simone Campanoni, Giovanni Agosta, Stefano Crespi-...
CN
2004
148views more  CN 2004»
15 years 5 months ago
DSMCast: a scalable approach for DiffServ multicasting
One of the dominant questions facing the Internet today is, how can the network meet the needs of the users and their applications (QoS) while trying to keep such implementations s...
Aaron Striegel, G. Manimaran
CLUSTER
2002
IEEE
15 years 5 months ago
File and Object Replication in Data Grids
Data replication is a key issue in a Data Grid and can be managed in different ways and at different levels of granularity: for example, at the file level or object level. In the ...
Heinz Stockinger, Asad Samar, Koen Holtman, Willia...
150
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MICRO
2000
IEEE
72views Hardware» more  MICRO 2000»
15 years 5 months ago
PipeRench implementation of the instruction path coprocessor
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John ...
MICRO
2002
IEEE
121views Hardware» more  MICRO 2002»
15 years 5 months ago
Convergent scheduling
Convergent scheduling is a general framework for instruction scheduling and cluster assignment for parallel, clustered architectures. A convergent scheduler is composed of many ind...
Walter Lee, Diego Puppin, Shane Swenson, Saman P. ...