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DATE
2005
IEEE
109views Hardware» more  DATE 2005»
14 years 1 months ago
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qua...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
DNA
2006
Springer
130views Bioinformatics» more  DNA 2006»
13 years 9 months ago
Displacement Whiplash PCR: Optimized Architecture and Experimental Validation
Whiplash PCR-based methods of biomolecular computation (BMC), while highly-versatile in principle, are well-known to suffer from a simple but serious form of self-poisoning known a...
John A. Rose, Ken Komiya, Satsuki Yaegashi, Masami...
CATA
2003
13 years 8 months ago
Implementation and Performance Evaluation of Intel VTUNE Image Processing Functions in the MATLAB Environment
Many current general purpose processors use extensions to the instruction set architecture to enhance the performance of digital image processing and multimedia applications. In t...
Phaisit Chewputtanagul, David Jeff Jackson, Kennet...
ICC
2007
IEEE
107views Communications» more  ICC 2007»
14 years 1 months ago
The SILO Architecture for Services Integration, controL, and Optimization for the Future Internet
— We propose a new internetworking architecture that represents a departure from current philosophy and practice, as a contribution to the ongoing debate regarding the future Int...
Rudra Dutta, George N. Rouskas, Ilia Baldine, Arno...
CASES
2005
ACM
13 years 9 months ago
Architectural support for real-time task scheduling in SMT processors
In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architec...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...