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MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 1 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
CODES
2007
IEEE
14 years 1 months ago
A code-generator generator for multi-output instructions
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...
Hanno Scharwächter, Jonghee M. Youn, Rainer L...
PPOPP
2005
ACM
14 years 28 days ago
Fault tolerant high performance computing by a coding approach
As the number of processors in today’s high performance computers continues to grow, the mean-time-to-failure of these computers are becoming significantly shorter than the exe...
Zizhong Chen, Graham E. Fagg, Edgar Gabriel, Julie...
SDL
2007
192views Hardware» more  SDL 2007»
13 years 8 months ago
OpenComRTOS: An Ultra-Small Network Centric Embedded RTOS Designed Using Formal Modeling
Abstract. OpenComRTOS is one of the few Real-Time Operating Systems (RTOS) for embedded systems that was developed using formal modeling techniques. The goal was to obtain a proven...
Eric Verhulst, Gjalt G. de Jong
ISPASS
2006
IEEE
14 years 1 months ago
Modeling TCAM power for next generation network devices
Applications in Computer Networks often require high throughput access to large data structures for lookup and classification. Many advanced algorithms exist to speed these searc...
Banit Agrawal, Timothy Sherwood