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» Architectural Support for Synchronous Task Communication
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HPCA
2011
IEEE
12 years 11 months ago
MOPED: Orchestrating interprocess message data on CMPs
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Su...
SBCCI
2003
ACM
213views VLSI» more  SBCCI 2003»
14 years 23 days ago
Algorithms and Tools for Network on Chip Based System Design
Network on Chip (NoC) is a new paradigm for designing core based System on Chips. It supports high degree of reusability and is scalable. In this paper, an efficient Two-Step Gene...
Tang Lei, Shashi Kumar
SC
2009
ACM
14 years 2 months ago
Kepler + Hadoop: a general architecture facilitating data-intensive applications in scientific workflow systems
MapReduce provides a parallel and scalable programming model for data-intensive business and scientific applications. MapReduce and its de facto open source project, called Hadoop...
Jianwu Wang, Daniel Crawl, Ilkay Altintas
CORR
2007
Springer
114views Education» more  CORR 2007»
13 years 7 months ago
SWI-Prolog and the Web
Prolog is an excellent tool for representing and manipulating data written in formal languages as well as natural language. Its safe semantics and automatic memory management make...
Jan Wielemaker, Zhisheng Huang, Lourens van der Me...
DAC
1997
ACM
13 years 11 months ago
COSYN: Hardware-Software Co-Synthesis of Embedded Systems
: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power and cost goals. In t...
Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. J...