Abstract. Future communication and computation devices require mechanisms for on-the-fly reconfiguration in their protocol stack to operate in different situations and networks. Th...
In this paper we propose a hardware real time operating system (HW-RTOS) that implements the OS layer in a dual-processor SMP architecture. Intertask communication is specified b...
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
This paper presents the porting of an RTOS Micro C/OS-II on a novel reconfigurable instruction cell based architecture which fills the gap between DSP, FPGA and ASIC with high per...
Han Wei, Mark Muir, Ioannis Nousias, Tughrul Arsla...
One of the challenges in designing distributed, embedded systems is the paucity of formal, executable specification notations that provide support for both real-time and asynchron...