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» Architectural approaches to reduce leakage energy in caches
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HPCA
2007
IEEE
14 years 10 months ago
Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...
Kiran Puttaswamy, Gabriel H. Loh
DAC
2005
ACM
14 years 10 months ago
Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC
As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival prob...
Sorin Manolache, Petru Eles, Zebo Peng
ISCA
2007
IEEE
111views Hardware» more  ISCA 2007»
14 years 4 months ago
Express virtual channels: towards the ideal interconnection fabric
Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the per...
Amit Kumar 0002, Li-Shiuan Peh, Partha Kundu, Nira...
HPDC
2006
IEEE
14 years 3 months ago
Path Grammar Guided Trace Compression and Trace Approximation
Trace-driven simulation is an important technique used in the evaluation of computer architecture innovations. However using it for studying parallel computers and applications is...
Xiaofeng Gao, Allan Snavely, Larry Carter
ECRTS
2010
IEEE
13 years 11 months ago
Making DRAM Refresh Predictable
Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Sched...
Balasubramanya Bhat, Frank Mueller