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ASPDAC
2008
ACM
94views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architec...
Sujan Pandey, Rolf Drechsler
ISCA
2002
IEEE
127views Hardware» more  ISCA 2002»
14 years 23 days ago
The Optimum Pipeline Depth for a Microprocessor
The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing ar...
Allan Hartstein, Thomas R. Puzak
HPCA
1997
IEEE
14 years 1 days ago
Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems
Many parallel systems offer a simple view of memory: all storage cells are addresseduniformly. Despite a uniform view of the memory, the machines differsignificantly in theirmemo...
Thomas Stricker, Thomas R. Gross
HPCA
2003
IEEE
14 years 8 months ago
Active I/O Switches in System Area Networks
We present an active switch architecture to improve the performance of systems connected via system area networks. Our programmable active switches not only flexibly route packets...
Ming Hao, Mark Heinrich
IEEEPACT
2003
IEEE
14 years 1 months ago
Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on a General-Purpose CPU
Graphics and media processing is quickly emerging to become one of the key computing workloads. Programmable graphics processors give designers extra flexibility by running a sma...
Mauricio Breternitz Jr., Herbert H. J. Hum, Sanjee...