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» Architectural dependability evaluation with Arcade
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CODES
2004
IEEE
13 years 11 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
PDP
2011
IEEE
12 years 11 months ago
Quantifying Thread Vulnerability for Multicore Architectures
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
Isil Oz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir...
ISPASS
2008
IEEE
14 years 1 months ago
Metrics for Architecture-Level Lifetime Reliability Analysis
Abstract— This work concerns metrics for evaluating microarchitectural enhancements to improve processor lifetime reliability. A commonly reported reliability metric is mean time...
Pradeep Ramachandran, Sarita V. Adve, Pradip Bose,...
COOPIS
2004
IEEE
13 years 11 months ago
Evaluation of a Group Communication Middleware for Clustered J2EE Application Servers
Abstract. Clusters have become the de facto platform to scale J2EE application servers. Each tier of the server uses group communication to maintain consistency between replicated ...
Takoua Abdellatif, Emmanuel Cecchet, Renaud Lachai...
EUROSYS
2009
ACM
14 years 4 months ago
Pointless tainting?: evaluating the practicality of pointer tainting
This paper evaluates pointer tainting, an incarnation of Dynamic Information Flow Tracking (DIFT), which has recently become an important technique in system security. Pointer tai...
Asia Slowinska, Herbert Bos