Sciweavers

268 search results - page 16 / 54
» Architectural descriptions for FPGA circuits
Sort
View
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
14 years 1 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
DAC
2005
ACM
13 years 10 months ago
Exploring technology alternatives for nano-scale FPGA interconnects
Field Programmable Gate Arrays (FPGAs) are becoming increasingly popular. With their regular structures, they are particularly amenable to scaling to smaller technologies. On the ...
Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane I...
ICNP
2009
IEEE
14 years 3 months ago
Better by a HAIR: Hardware-Amenable Internet Routing
—Routing protocols are implemented in the form of software running on a general-purpose microprocessor. However, conventional software-based router architectures face significan...
Firat Kiyak, Brent Mochizuki, Eric Keller, Matthew...
FPGA
1999
ACM
142views FPGA» more  FPGA 1999»
14 years 29 days ago
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems
Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we addr...
Abdel Ejnioui, N. Ranganathan
FPL
2007
Springer
127views Hardware» more  FPL 2007»
14 years 2 months ago
Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications
This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific informatio...
Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wa...