268 search results - page 43 / 54 » Architectural descriptions for FPGA circuits |
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Digital Down Conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algo...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Combinational circuits are generally thought of as acyclic structures. It is known that cyclic structures can be combinational, and techniques have been proposed to analyze cyclic...
IEEECIT
2010
IEEE
13 years 6 months ago
2010
IEEE
- The increase of embedded applications complexity has demanded hardware more flexible while providing higher performance. Reconfigurable architectures and stream processing have b...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
Acyclic partitioning on combinational boolean networks has wide range of applications, from multiple FPGA chip partitioning to parallel circuit simulation. In this paper, we prese...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
Recent results indicate that functional test pattern generation (TPG) techniques may provide better defect coverages than do traditional logic-level techniques. Functional TPG alg...