20 search results - page 3 / 4 » Architectural evaluation of 3D stacked RRAM caches |
ISCA
2008
IEEE
14 years 2 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
3DIM
2007
IEEE
14 years 2 months ago
2007
IEEE
The ICP (Iterative Closest Point) algorithm is the de facto standard for geometric alignment of threedimensional models when an initial relative pose estimate is available. The ba...
HPCA
1997
IEEE
14 years 19 days ago
1997
IEEE
Many parallel systems offer a simple view of memory: all storage cells are addresseduniformly. Despite a uniform view of the memory, the machines differsignificantly in theirmemo...
ISLPED
2010
ACM
13 years 8 months ago
2010
ACM
Memories play a key role in FGPAs in the forms of both programming bits and embedded memory blocks. FPGAs using non-volatile memories have been the focus of attention with zero bo...
MICRO
2009
IEEE
14 years 3 months ago
2009
IEEE
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...