110 search results - page 13 / 22 » Architectural simulation for a programmable DSP chip set |
DAC
2003
ACM
14 years 8 months ago
2003
ACM
The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) sim...
GECCO
2007
Springer
14 years 1 months ago
2007
Springer
This work presents a novel approach to filter synthesis on a field programmable analog array (FPAA) architecture using a genetic algorithm (GA). First, a Matlab model of the FPA...
GLVLSI
1998
IEEE
13 years 11 months ago
1998
IEEE
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
SEUS
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper we present a distributed Hardware-in-the-Loop (HiL) simulation approach that supports the verification and validation activities in an integrated architecture as rec...
PPOPP
2006
ACM
14 years 1 months ago
2006
ACM
As multi-core architectures with Thread-Level Speculation (TLS) are becoming better understood, it is important to focus on TLS compilation. TLS compilers are interesting in that,...