110 search results - page 16 / 22 » Architectural simulation for a programmable DSP chip set |
TVLSI
2008
2008
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
13 years 7 months ago
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
CODES
2008
IEEE
14 years 1 months ago
2008
IEEE
The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid perfor...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
—This paper presents work on ultra-low-power circuits for brain–machine interfaces with applications for paralysis prosthetics, stroke, Parkinson’s disease, epilepsy, prosthe...
ARITH
2001
IEEE
13 years 11 months ago
2001
IEEE
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...
IJCNN
2007
IEEE
14 years 1 months ago
2007
IEEE
- We present an application of a massively parallel processor array VLSI circuit to the implementation of neural networks in complex architectural arrangements. The work was motiva...