110 search results - page 8 / 22 » Architectural simulation for a programmable DSP chip set |
ISMVL
2000
IEEE
13 years 11 months ago
2000
IEEE
Evolvable Hardware (EHW) refers to HW design and self-reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, comments o...
VLSISP
2008
13 years 7 months ago
2008
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the e...
EH
1999
IEEE
13 years 11 months ago
1999
IEEE
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reco...
IAJIT
2010
13 years 6 months ago
2010
: A new code sign implementation of vector median rational hybrid filter based on efficient hardware/software implementation is introduced and applied to colour image filtering pro...