Bandwidth-Constrained Mapping of Cores onto NoC Architectures

We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the edge of congestion. Typical applications are in the area of multi-media processing. We consider a meshbased Networks on Chip (NoC) architecture, and we explore the assignment of cores to mesh cross-points so that the traffic on links satisfies bandwidth constraints. A single-path deterministic routing between the cores places high bandwidth demands on the links. The bandwidth requirements can be significantly reduced by splitting the traffic between the cores across multiple paths. In this paper, we present NMAP, a fast algorithm that maps the cores onto a mesh NoC architecture under bandwidth constraints, minimizing the average communication delay. The NMAP algorithm is presented for both single minimum-path routing and splittraffic routing. The algorithm is applied to a benchmark DSP design and the resulting...

• Type: Conference
• Year: 2004
• Where: DATE
• Authors: Srinivasan Murali, Giovanni De Micheli
• Keywords: Bandwidth Constraints, Cores, DATE 2004, Hardware, NMAP Algorithm