113 search results - page 7 / 23 » Architectural-Level Fault Tolerant Computation in Nanoelectr... |
ET
2008
13 years 7 months ago
2008
Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware harde...
DSN
2002
IEEE
14 years 13 days ago
2002
IEEE
The architecture and implementation of the LEON-FT processor is presented. LEON-FT is a fault-tolerant 32-bit processor based on the SPARC V8 instruction set. The processors toler...
DDECS
2007
IEEE
14 years 1 months ago
2007
IEEE
– The implementation and the fault simulation technique for the highly reliable digital design using two FPGAs under a processor control is presented. Two FPGAs are used for dupl...
IPPS
1999
IEEE
13 years 11 months ago
1999
IEEE
In this paper we consider general simulations of algorithms designed for fully operational BSP and CGM machines on machines with faulty processors. The faults are deterministic (i...
DSN
2005
IEEE
13 years 9 months ago
2005
IEEE
The increasing transient fault rate will necessitate onchip fault tolerance techniques in future processors. The speed gap between the processor and the memory is also increasing,...