Most approaches in reverse engineering literature generate a single view of a software system that restricts the scope of the reconstruction process. We propose an orchestrated se...
We present the design and implementation of the Janus1 architecture for providing flexible and lightweight access to sensor network resources from Internet-type networks. Janus p...
Time-triggered architectures (TTAs) are strong candidate platforms for safety-critical real-time applications. A typical time-triggered architecture is constituted by one or more ...
Kathy Dang Nguyen, P. S. Thiagarajan, Weng-Fai Won...
Recently, platform FPGAs that integrate sequential processors with a spatial fabric have become prevalent. While these hybrid architectures ease the burden of integrating sequenti...
Network on Chip (NoC) is a new paradigm for designing core based System on Chips. It supports high degree of reusability and is scalable. In this paper, an efficient Two-Step Gene...