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ASAP
2006
IEEE
138views Hardware» more  ASAP 2006»
15 years 8 months ago
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper pr...
Marjan Karkooti, Predrag Radosavljevic, Joseph R. ...
RSP
2008
IEEE
120views Control Systems» more  RSP 2008»
15 years 10 months ago
Co-design Architecture and Implementation for Point-Based Rendering on FPGAs
Current graphic cards include advanced graphic processing units to accelerate the rendering of 3D objects with millions of polygons. As object models grow in complexity, the rende...
Mateusz Majer, Stefan Wildermann, Josef Angermeier...
LANOMS
2007
IEEE
172views Education» more  LANOMS 2007»
15 years 10 months ago
Implementing and Deploying Network Monitoring Service Oriented Architectures
—Recently there is a growing interest in accessing network measurement and status data across multiple domains, in order to detect eventual network problems which can hinder the ...
Leobino Nascimento Sampaio, Ivo Koga, Rafael Costa...
DL
1995
Springer
143views Digital Library» more  DL 1995»
15 years 7 months ago
Digital Libraries: Issues and Architectures
The research field of digital libraries must be viewed as a union of subfields from a variety of domains combined with new research issues in order to realize its full potential....
Peter J. Nürnberg, Richard Furuta, John J. Le...
ICLP
2001
Springer
15 years 8 months ago
PALS: An Or-Parallel Implementation of Prolog on Beowulf Architectures
This paper describes the development of the PALS system, an implementation of Prolog that efficiently exploits or-parallelism on share-nothing platforms. PALS makes use of a novel ...
Karen Villaverde, Enrico Pontelli, Hai-Feng Guo, G...