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INTEGRATION
2007
98views more  INTEGRATION 2007»
15 years 4 months ago
Hashchip: A shared-resource multi-hash function processor architecture on FPGA
The ubiquitous presence of mobile devices and the demand for better performance and efficiency have motivated research into embedded implementations of cryptography algorithms. I...
T. S. Ganesh, Michael T. Frederick, T. S. B. Sudar...
TMM
2002
81views more  TMM 2002»
15 years 4 months ago
Staggered push - a linearly scalable architecture for push-based parallel video servers
With the rapid performance improvements in low-cost PCs, it becomes increasingly practical and cost-effective to implement large-scale video-on-demand (VoD) systems around parallel...
Jack Y. B. Lee
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
15 years 4 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
VLSID
2007
IEEE
99views VLSI» more  VLSID 2007»
16 years 4 months ago
Low Power Implementation for Minimum Norm Sorting and Block Upper Tri-angularization of Matrices used in MIMO Wireless Systems
Multiple Input - Multiple Output (MIMO) wireless technology involves highly complex vectors and matrix computations which are directly related to increased power and area consumpt...
Zahid Khan, Tughrul Arslan, John S. Thompson, Ahme...
DSN
2000
IEEE
15 years 9 months ago
Implementing e-Transactions with Asynchronous Replication
ts the abstraction of e-Transactions in three-tier architectures. Three-tier architectures are typically Internetoriented architectures, where the end-user interacts with frontend ...
Svend Frølund, Rachid Guerraoui