218 search results - page 29 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
FPGA
2006
ACM
14 years 20 days ago
2006
ACM
This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for FieldProgrammable Gate Arrays (FPGA's). The paper begins...
RSP
2008
IEEE
14 years 3 months ago
2008
IEEE
ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based im...
DAC
2008
ACM
14 years 10 months ago
2008
ACM
We present a domain-specific approach to representing datapaths for hardware implementations of linear signal transform algorithms. We extend the tensor structure for describing l...
ISLPED
2009
ACM
14 years 3 months ago
2009
ACM
An energy efficient object recognition processor is proposed for real-time visual applications. Its energy efficiency is improved by lowering average power consumption while susta...
IPPS
2006
IEEE
14 years 3 months ago
2006
IEEE
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...