218 search results - page 5 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
TECS
2008
13 years 7 months ago
2008
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
ANCS
2006
ACM
14 years 1 months ago
2006
ACM
A large body of research literature has focused on improving the performance of longest prefix match IP-lookup. More recently, embedded memory based architectures have been propos...
EUROMICRO
2000
IEEE
14 years 4 days ago
2000
IEEE
We propose a design flow for low-power and low-cost, data-dominated, embedded systems which tightly integrate different technologies and architectures. We use Mathworks’ Simuli...
FPGA
2004
ACM
14 years 1 months ago
2004
ACM
In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of regist...
DAC
1997
ACM
13 years 12 months ago
1997
ACM
A methodology for architecture exploration of look-up table based decoders is presented. For the degree of parallel processing a trade-off can be made by exploring system level an...