1381 search results - page 105 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
MMB
2012
Springer
12 years 3 months ago
2012
Springer
Abstract. During development, processor architectures can be tuned and configured by many different parameters. For benchmarking, automatic design space explorations (DSEs) with h...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
IEEESCC
2010
IEEE
14 years 4 days ago
2010
IEEE
Abstract—Modern service-oriented systems have increasingly complex loosely-coupled architectures that often exhibit poor performance and resource efficiency and have high operat...
DAC
2003
ACM
14 years 9 months ago
2003
ACM
Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best pow...
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
Sorting is a commonly used process with a wide breadth of applications in the high performance computing field. Early research in parallel processing has provided us with comprehen...