1381 search results - page 15 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
ECCTD
2011
12 years 7 months ago
2011
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
CONEXT
2009
ACM
13 years 9 months ago
2009
ACM
In enterprise and data center networks, the scalability of the data plane becomes increasingly challenging as forwarding tables and link speeds grow. Simply building switches with...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
ABSTRACT: An active leakage-injection scheme (ALIS) for lowvoltage (LV) high-density (HD) SRAMs is presented. By means of a feedback loop comprising a servo-amplifier and a commond...
TVLSI
2010
13 years 2 months ago
2010
Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve ...
VLSID
2004
IEEE
14 years 8 months ago
2004
IEEE
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...