Sciweavers

1381 search results - page 32 / 277
» Architecture and Design of a High Performance SRAM for SOC D...
Sort
View
MICRO
2003
IEEE
152views Hardware» more  MICRO 2003»
14 years 1 months ago
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...
Shubhendu S. Mukherjee, Christopher T. Weaver, Joe...
SDL
2003
147views Hardware» more  SDL 2003»
13 years 9 months ago
Modelling and Evaluation of a Network on Chip Architecture Using SDL
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
Rickard Holsmark, Magnus Högberg, Shashi Kuma...
AC
1999
Springer
13 years 7 months ago
Architectures and patterns for developing high performance real-time ORB endsystems
Many types of applications can benefit from flexible and open middleware. CORBA is an emerging middleware standard for Object Request Brokers (ORBs) that simplifies the developmen...
Douglas C. Schmidt, David L. Levine, Chris Clevela...
ICMCS
2005
IEEE
104views Multimedia» more  ICMCS 2005»
14 years 1 months ago
A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...
Grzegorz Pastuszak
SIGCOMM
2009
ACM
14 years 2 months ago
BCube: a high performance, server-centric network architecture for modular data centers
This paper presents BCube, a new network architecture specifically designed for shipping-container based, modular data centers. At the core of the BCube architecture is its serve...
Chuanxiong Guo, Guohan Lu, Dan Li, Haitao Wu, Xuan...