1381 search results - page 66 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
RTAS
2010
IEEE
13 years 6 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...
CLUSTER
2006
IEEE
14 years 2 months ago
2006
IEEE
Clusters are the most common solutions for high performance computing at the present time. In this kind of systems, an important challenge is the I/O subsystem design. Typically, ...
CONPAR
1994
14 years 7 days ago
1994
The Rewrite Rule Machine (RRM) is a massively parallel MIMD/SIMD computer designed with the explicit purpose of supporting veryhigh-level parallel programming with rewrite rules. T...
CODES
2007
IEEE
14 years 2 months ago
2007
IEEE
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
There is an increasing need for obtaining a reasonably accurate estimate of energy dissipation in SoC designs. Array structures have a significant contribution to the total system...