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    IPPS
    2006
    IEEE
    122views Distributed And Parallel Com...» more  IPPS 2006»
    Multi-clock pipelined design of an IEEE 802.11a physical layer transmitter
    14 years 2 months ago
    Multi-clock pipelined design of an IEEE 802.11a physical layer transmitter
    Download  www.cecs.uci.edu
    Among different wireless LAN technologies 802.11a has recently become popular due to its high throughput, large system capacity, and relatively long range. In this paper, we prop...
    Maryam Mizani, Daler N. Rakhmatov
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    CASES
    2006
    ACM
    117views System Software» more  CASES 2006»
    Efficient architectures through application clustering and architectural heterogeneity
    13 years 12 months ago
    Efficient architectures through application clustering and architectural heterogeneity
    Download  www.eecs.harvard.edu
    Customizing architectures for particular applications is a promising approach to yield highly energy-efficient designs for embedded systems. This work explores the benefits of arc...
    Lukasz Strozek, David Brooks
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    FPGA
    2006
    ACM
    141views FPGA» more  FPGA 2006»
    A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
    13 years 12 months ago
    A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
    Download  pavel.physics.sunysb.edu
    This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...
    Dmitri B. Strukov, Konstantin Likharev
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    HPCA
    2009
    IEEE
    174views Distributed And Parallel Com...» more  HPCA 2009»
    Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics
    14 years 8 months ago
    Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics
    Download  www.ece.lsu.edu
    The shrinking processor feature size, lower threshold voltage and increasing clock frequency make modern processors highly vulnerable to transient faults. Architectural Vulnerabil...
    Lide Duan, Bin Li, Lu Peng
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    ASAP
    2006
    IEEE
    130views Hardware» more  ASAP 2006»
    Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
    14 years 2 months ago
    Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
    Download  www.ivgroup.ee.ucla.edu
    Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
    Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
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