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AHS
2006
IEEE
142views Hardware» more  AHS 2006»
14 years 2 months ago
On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition
To increase the flexibility of single-chip evolvable hardware systems, we explore possibilities of systems with the evolutionary algorithm implemented in software on an onchip pr...
Kyrre Glette, Jim Torresen, Moritoshi Yasunaga, Yo...
FPL
2008
Springer
254views Hardware» more  FPL 2008»
13 years 10 months ago
Digital hilbert transformers for FPGA-based phase-locked loops
The phase detector is a main building block in phaselocked loop (PLL) applications. FPGAs permit the realtime implementation of the CORDIC algorithm which offers an efficient solu...
Martin Kumm, M. Shahab Sanjari
IPPS
1999
IEEE
14 years 1 months ago
PM-PVM: A Portable Multithreaded PVM
PM-PVM is a portable implementation of PVM designed to work on SMP architectures supporting multithreading. PM-PVM portability is achieved through the implementation of the PVM fu...
Claudio M. P. Santos, Júlio S. Aude
ICDE
2001
IEEE
104views Database» more  ICDE 2001»
14 years 10 months ago
Bundles in Captivity: An Application of Superimposed Information
What do you do to make sense of a mass of information on a given topic? Paradoxically, you likely add yet more information to the pile: annotations, underlining, bookmarks, cross-...
Lois M. L. Delcambre, David Maier, Shawn Bowers, M...
DAC
2006
ACM
14 years 9 months ago
A new hybrid FPGA with nanoscale clusters and CMOS routing
In this paper we propose a hybrid FPGA using nanoscale clusters with an architecture similar to clusters of traditional CMOS FPGAs. The proposed cluster is made of a crossbar of n...
Reza M. Rad, Mohammad Tehranipoor