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» Architecture and synthesis for multi-cycle communication
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DAC
2004
ACM
14 years 8 months ago
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory
Massive data transfer encountered in emerging multimedia embedded applications requires architecture allowing both highly distributed memory structure and multiprocessor computati...
Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik...
ICC
2007
IEEE
102views Communications» more  ICC 2007»
14 years 1 months ago
A Scalable Wireless Channel Emulator for Broadband MIMO Systems
: This paper addresses the issue of designing scalable prototypes for multi input multi output (MIMO) wireless channel emulation. To date, emulators are extending single input sing...
Hamid Eslami, Ahmed M. Eltawil
EUROPAR
2001
Springer
14 years 4 days ago
Multiprocessor Clustering for Embedded Systems
Abstract. In this paper, we address two key trends in the synthesis of implementations for embedded multiprocessors — (1) the increasing importance of managing interprocessor com...
Vida Kianzad, Shuvra S. Bhattacharyya
ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
14 years 4 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
CODES
2006
IEEE
14 years 1 months ago
Automatic generation of transaction level models for rapid design space exploration
Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate suc...
Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rain...