72 search results - page 6 / 15 » Architecture evaluation for power-efficient FPGAs |
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony’s Playstation 2 vector units offer scope for hardware acceleration of applications. Implementin...
FPL
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. This paper presents a new scheme for the hardware evaluation of elementary functions, based on a piecewise second order minimax approximation. The novelty is that this ev...
ICES
2005
Springer
14 years 1 months ago
2005
Springer
A specialized architecture was developed and evaluated to evolve relatively large sorting networks in an ordinary FPGA. Genetic unit and fitness function are also implemented on t...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain F...
CC
2008
Springer
13 years 9 months ago
2008
Springer
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...