193 search results - page 34 / 39 » Architecture for a Non-deterministic Simulation Machine |
ICS
2004
Tsinghua U.
14 years 1 months ago
2004
Tsinghua U.
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
ARVLSI
1997
IEEE
14 years 5 days ago
1997
IEEE
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
PPOPP
2010
ACM
14 years 5 months ago
2010
ACM
Most modern Chip Multiprocessors (CMP) feature shared cache on chip. For multithreaded applications, the sharing reduces communication latency among co-running threads, but also r...
VTC
2007
IEEE
14 years 2 months ago
2007
IEEE
— Hydra is a flexible wireless network testbed being developed at UT Austin. Our focus is networks that support multiple wireless hops and where the network, especially the MAC,...
DAMAS
2005
Springer
14 years 1 months ago
2005
Springer
We present a novel cognitive agent architecture and demonstrate its effectiveness in the Sense and Respond Logistics (SRL) domain. Effective applications to support SRL must antic...