Sciweavers

19776 search results - page 3742 / 3956
» Architecture of a Database System
Sort
View
CGO
2005
IEEE
15 years 9 months ago
Maintaining Consistency and Bounding Capacity of Software Code Caches
Software code caches are becoming ubiquitous, in dynamic optimizers, runtime tool platforms, dynamic translators, fast simulators and emulators, and dynamic compilers. Caching fre...
Derek Bruening, Saman P. Amarasinghe
CODES
2005
IEEE
15 years 9 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra
CODES
2005
IEEE
15 years 9 months ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
15 years 9 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
HT
2005
ACM
15 years 9 months ago
Processing link structures and linkbases in the web's open world linking
Hyperlinks are an essential feature of the World Wide Web, highly responsible for its success. XLink improves on HTML’s linking capabilities in several ways. In particular, link...
François Bry, Michael Eckert
« Prev « First page 3742 / 3956 Last » Next »