Sciweavers

19776 search results - page 3887 / 3956
» Architecture of a Database System
Sort
View
HPCA
2003
IEEE
14 years 9 months ago
TCP: Tag Correlating Prefetchers
Although caches for decades have been the backbone of the memory system, the speed gap between CPU and main memory suggests their augmentation with prefetching mechanisms. Recentl...
Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras
HPCA
2003
IEEE
14 years 9 months ago
Slipstream Execution Mode for CMP-Based Multiprocessors
Scalability of applications on distributed sharedmemory (DSM) multiprocessors is limited by communication overheads. At some point, using more processors to increase parallelism y...
Khaled Z. Ibrahim, Gregory T. Byrd, Eric Rotenberg
HPCA
2003
IEEE
14 years 9 months ago
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
Increasing focus on power dissipation issues in current microprocessors has led to a host of proposals for clock gating and other power-saving techniques. While generally effectiv...
Russ Joseph, David Brooks, Margaret Martonosi
POPL
2003
ACM
14 years 9 months ago
Bitwidth aware global register allocation
Multimedia and network processing applications make extensive use of subword data. Since registers are capable of holding a full data word, when a subword variable is assigned a r...
Sriraman Tallam, Rajiv Gupta
MOBISYS
2008
ACM
14 years 8 months ago
Symphony: synchronous two-phase rate and power control in 802.11 wlans
Adaptive transmit power control in 802.11 Wireless LANs (WLANs) on a per-link basis helps increase network capacity and improves battery life of Wifi-enabled mobile devices. Howev...
Kishore Ramachandran, Ravi Kokku, Honghai Zhang, M...
« Prev « First page 3887 / 3956 Last » Next »