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» Architectures for function evaluation on FPGAs
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ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
14 years 1 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
MSWIM
2006
ACM
14 years 1 months ago
An application-driven perspective on wireless sensor network security
Wireless sensor networks (WSNs) have recently attracted a lot of interest due to the range of applications they enable. Unfortunately, WSNs are exposed to numerous security threat...
Eric Sabbah, Adnan Majeed, Kyoung-Don Kang, Ke Liu...
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
14 years 1 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
GI
2005
Springer
14 years 1 months ago
Distributed User Modeling for Situated Interaction
: A distributed service to model and control contextual information in mobile and ubiquitous computing environments is presented in this paper. We introduce the general user model ...
Dominik Heckmann
ICCS
2005
Springer
14 years 1 months ago
Managing Heterogeneity in a Grid Parallel Haskell
Computational Grids potentially offer cheap large-scale high-performance systems, but are a very challenging architecture, being heterogeneous, shared and hierarchical. Rather tha...
Abdallah Al Zain, Philip W. Trinder, Hans-Wolfgang...