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» Architectures for function evaluation on FPGAs
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FPGA
2008
ACM
163views FPGA» more  FPGA 2008»
13 years 9 months ago
TORCH: a design tool for routing channel segmentation in FPGAs
A design tool for routing channel segmentation in islandstyle FPGAs is presented. Given the FPGA architecture parameters and a set of benchmark designs, the tool optimizes routing...
Mingjie Lin, Abbas El Gamal
IJNSEC
2007
137views more  IJNSEC 2007»
13 years 7 months ago
An FPGA-based AES-CCM Crypto Core For IEEE 802.11i Architecture
The widespread adoption of IEEE 802.11 wireless networks has brought its security paradigm under active research. One of the important research areas in this field is the realiza...
Arshad Aziz, Nassar Ikram
DAC
2003
ACM
14 years 8 months ago
Generalized cofactoring for logic function evaluation
Yunjian Jiang, Slobodan Matic, Robert K. Brayton
FPGA
2001
ACM
123views FPGA» more  FPGA 2001»
14 years 6 days ago
Matching and searching analysis for parallel hardware implementation on FPGAs
Matching and searching computations play an important role in the indexing of data. These computations are typically encoded in very tight loops with a single index variable and a...
Pablo Moisset, Pedro C. Diniz, Joonseok Park
ARC
2009
Springer
134views Hardware» more  ARC 2009»
14 years 11 days ago
A HyperTransport 3 Physical Layer Interface for FPGAs
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
Heiner Litz, Holger Fröning, Ulrich Brün...