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» Architectures for function evaluation on FPGAs
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FPGA
2003
ACM
117views FPGA» more  FPGA 2003»
14 years 28 days ago
PipeRoute: a pipelining-aware router for FPGAs
We present a pipelining-aware router for FPGAs. The problem of routing pipelined signals is different from the conventional FPGA routing problem. For example, the two terminal N-D...
Akshay Sharma, Carl Ebeling, Scott Hauck
FPGA
2008
ACM
142views FPGA» more  FPGA 2008»
13 years 9 months ago
Modeling routing demand for early-stage FPGA architecture development
Architecture development for FPGAs has typically been a very empirical discipline, requiring the synthesis of benchmark circuits into candidate architectures. This is difficult to...
Wei Mark Fang, Jonathan Rose
FPGA
2000
ACM
141views FPGA» more  FPGA 2000»
13 years 11 months ago
Tolerating operational faults in cluster-based FPGAs
In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain ...
Vijay Lakamraju, Russell Tessier
MSE
2005
IEEE
133views Hardware» more  MSE 2005»
14 years 1 months ago
Embedded System Design with FPGAs Using HDLs (Lessons Learned and Pitfalls to Be Avoided)
This paper describes the authors experience with teaching VHDL (and more recently, Verilog) to undergraduate and graduate students at WPI and to engineers through various short co...
R. James Duckworth
FCCM
2007
IEEE
107views VLSI» more  FCCM 2007»
14 years 2 months ago
Optimizing Logarithmic Arithmetic on FPGAs
This paper proposes optimizations of the methods and parameters used in both mathematical approximation and hardware design for logarithmic number system (LNS) arithmetic. First, ...
Haohuan Fu, Oskar Mencer, Wayne Luk