643 search results - page 45 / 129 » Architectures for function evaluation on FPGAs |
EUROPAR
1999
Springer
14 years 2 months ago
1999
Springer
Abstract. The High Performance Fortran (HPF) benchmark suite HPFBench was designed for evaluating the HPF language and compilers on scalable architectures. The functionality of the...
DATE
2009
IEEE
14 years 5 months ago
2009
IEEE
As the number of cores continues to grow in both digital signal and general purpose processors, tools which perform automatic scheduling from model-based designs are of increasing...
CODES
2007
IEEE
14 years 4 months ago
2007
IEEE
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
IPPS
1998
IEEE
14 years 1 months ago
1998
IEEE
We compare the performance of systems consisting of one large cluster containing q processors with systems where processors are grouped into k clusters containing u processors eac...
ISICT
2003
13 years 11 months ago
2003
Historically, a typical avionics system architecture has been designed as a federated architecture of black-boxes with well-defined functions and implemented on fully dedicated co...