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» Architectures for function evaluation on FPGAs
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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 10 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
ICDCS
2000
IEEE
14 years 2 months ago
Quartz: A QoS Architecture for Open Systems
This paper describes an architecture that provides support for quality of service (QoS) specification and enforcement in heterogeneous distributed computing systems. The Quartz Qo...
Frank Siqueira, Vinny Cahill
ICSEA
2007
IEEE
14 years 4 months ago
An Access Control Metamodel for Web Service-Oriented Architecture
— With the mutual consent to use WSDL (Web Service Description Language) to describe web service interfaces and SOAP as the basic communication protocol, the cornerstone for web ...
Christian Emig, Frank Brandt, Sebastian Abeck, J&u...
DAC
2010
ACM
13 years 10 months ago
RAMP gold: an FPGA-based architecture simulator for multiprocessors
We present RAMP Gold, an economical FPGA-based architecture simulator that allows rapid early design-space exploration of manycore systems. The RAMP Gold prototype is a high-throu...
Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yun...
MOMPES
2009
IEEE
14 years 4 months ago
ArcheOpterix: An extendable tool for architecture optimization of AADL models
For embedded systems quality requirements are equally if not even more important than functional requirements. The foundation for the fulfillment of these quality requirements ha...
Aldeida Aleti, Stefan Björnander, Lars Grunsk...