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» Architectures for function evaluation on FPGAs
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INFOCOM
2005
IEEE
14 years 1 months ago
Architecture and algorithms for an IEEE 802.11-based multi-channel wireless mesh network
— Even though multiple non-overlapped channels exist in the 2.4GHz and 5GHz spectrum, most IEEE 802.11-based multi-hop ad hoc networks today use only a single channel. As a resul...
Ashish Raniwala, Tzi-cker Chiueh
INFOCOM
1998
IEEE
14 years 3 days ago
Implementing Distributed Packet Fair Queueing in a Scalable Switch Architecture
To support the Internet's explosive growth and expansion into a true integrated services network, there is a need for cost-effective switching technologies that can simultaneo...
Donpaul C. Stephens, Hui Zhang
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
11 years 10 months ago
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures
A significant portion of the energy dissipated in modern integrated circuits is consumed by the overhead associated with timing guardbands that ensure reliable execution. Timing ...
Evgeni Krimer, Patrick Chiang, Mattan Erez
MOBICOM
2010
ACM
13 years 8 months ago
CTRL: a self-organizing femtocell management architecture for co-channel deployment
Femtocell technology has been drawing considerable attention as a cost-effective means of improving cellular coverage and capacity. However, under co-channel deployment, femtocell...
Ji-Hoon Yun, Kang G. Shin
SIGMETRICS
2008
ACM
181views Hardware» more  SIGMETRICS 2008»
13 years 7 months ago
Counter braids: a novel counter architecture for per-flow measurement
Fine-grained network measurement requires routers and switches to update large arrays of counters at very high link speed (e.g. 40 Gbps). A naive algorithm needs an infeasible amo...
Yi Lu, Andrea Montanari, Balaji Prabhakar, Sarang ...