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TASE
2008
IEEE
13 years 8 months ago
Modeling and Supervisory Control of Railway Networks Using Petri Nets
In this paper we deal with the problem of modeling railway networks with Petri nets so as to apply the theory of supervisory control for discrete event systems to automatically de...
Alessandro Giua, Carla Seatzu
ISCA
2005
IEEE
81views Hardware» more  ISCA 2005»
14 years 2 months ago
The Impact of Performance Asymmetry in Emerging Multicore Architectures
Performance asymmetry in multicore architectures arises when individual cores have different performance. Building such multicore processors is desirable because many simple cores...
Saisanthosh Balakrishnan, Ravi Rajwar, Michael Upt...
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
14 years 1 months ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
14 years 1 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for applicationāˆ’specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
HPCN
2000
Springer
14 years 10 days ago
An Analytical Model for a Class of Architectures under Master-Slave Paradigm
We build an analytical model for an application utilizing master-slave paradigm. In the model, only three architecture parameters are used: latency, bandwidth and flop rate. Instea...
Yasemin Yalçinkaya, Trond Steihaug