125 search results - page 22 / 25 » Area and delay trade-offs in the circuit and architecture de... |
DAC
2000
ACM
14 years 8 months ago
2000
ACM
This paper presents MINFLOTRANSIT, a new transistor sizing tool for fast sizing of combinational circuits with minimal cost. MINFLOTRANSIT is an iterative relaxation based tool th...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
VLSID
2008
IEEE
14 years 7 months ago
2008
IEEE
Negative Bias Temperature Instability (NBTI) has been identified as a major and critical reliability issue for PMOS devices in nano-scale designs. It manifests as a negative thres...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurabil...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
The gain-based technology mapping paradigm has been successfully employed for finding minimum delay and minimum area mappings. However, existing gain-based technology mappers fail...