43 search results - page 7 / 9 » Area optimization of multi-cycle operators in high-level syn... |
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
EURODAC
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper describes a method to optimize the performance of data paths. It is based on bit-level arithmetic transformations, and is especially suited to optimize large adder stru...
FPGA
2008
ACM
13 years 9 months ago
2008
ACM
Pattern-based synthesis has drawn wide interest from researchers who tried to utilize the regularity in applications for design optimizations. In this paper we present a general p...
VLSID
2006
IEEE
14 years 7 months ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
SIGCOMM
2009
ACM
14 years 1 months ago
2009
ACM
The routing architecture of the original 4.4BSD [3] kernel has been deployed successfully without major design modification for over 15 years. In the unified routing architectur...