29 search results - page 4 / 6 » Area-effective FIR filter design for multiplier-less impleme... |
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
APCCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— In recent years, several approaches have been proposed aiming the optimal joint design of finite impulse response (FIR) multiple-input multiple-output (MIMO) transmitter and r...
SBCCI
2009
ACM
14 years 6 days ago
2009
ACM
The multiplication of a variable by multiple constants, i.e., the multiple constant multiplications (MCM), has been a central operation and performance bottleneck in many applicat...
ISCAS
1994
IEEE
13 years 11 months ago
1994
IEEE
In this paper a new type of maximally decimated FIR cosine modulated filter banks is proposed. Each analysis and synthesis filter in this filter bank has linear phase. We can desig...
FPL
2008
Springer
13 years 9 months ago
2008
Springer
The phase detector is a main building block in phaselocked loop (PLL) applications. FPGAs permit the realtime implementation of the CORDIC algorithm which offers an efficient solu...